1. Field of the Invention
The present invention relates generally to power amplifiers, and particularly to Doherty power amplifiers.
2. Technical Background
One of the biggest challenges facing cellular base station power amplifier manufacturers is the task of increasing the efficiency of linear power amplifiers for high peak-to-average ratio (PAR) signals in a linear power amplifier. At same time, the competition on a global scale has created a requirement for base stations to support a wider range of frequency bands, as new spectrum is released worldwide to meet urgent capacity demands. Once the above stated challenge of providing a wideband power amplifier design is accomplished, designers can then focus on developing generic platforms that can be deployed in a number of different products with minimal or no change. Stated differently, a solution to the above stated problem reduces the number of design variants and this, in turn, provides the added benefit of faster design cycles and lower development costs.
In one approach that has been considered, Doherty power amplifiers have been widely adopted as a linear amplifier configuration with improved efficiency for high PAR signals. A Doherty power amplifier architecture includes two amplifiers. The input signal is directed into a device, such as a hybrid coupler, that provides in-phase and quadrature components of the input signal. Stated differently, the hybrid coupler splits the input signal into two equal halves, with the quadrature component being 90° out of phase with respect to the in-phase component. The first amplifier is referred to as the carrier amplifier or main amplifier (as it is referred to in all of the drawings) and it amplifies the in-phase component. The second amplifier is known as the peak amplifier (or peaking amplifier) and it is configured to amplify the quadrature component of the input signal. The carrier amplifier is typically implemented as a Class B amplifier that operates over approximately 180° of an input signal's sinusoidal period. The peak amplifier, on the other hand, is implemented as a Class C amplifier that is biased to operate in only a portion of the operating region of the carrier amplifier. Thus, only the carrier amplifier is operating when the input signal power is relatively low; and the output impedance of the peak amplifier is very high (e.g., 1000 Ohms).
In reference to FIGS. 1A-1B, a conventional Doherty architecture is depicted. In this example, a 2 GHz amplifier that employs a typical high power GaN transistor having an optimum output matching impedance of 6.25 ohms is depicted. An output matching network is included in the schematic such that overall system bandwidth can be demonstrated. The carrier amplifier is coupled to transmission line 1 and transmission line 2 which are disposed in series. The peaking amplifier is coupled to transmission line 4 and transmission line 5, which are also disposed in series. The phase delay of matching networks has to be two quarter wavelength to achieve required Doherty operation. The Doherty combiner therefore includes two quarter wavelength transmission lines 6 and 7. For illustration purposes, only the practical transistor parasitic are ignored, and the matching networks are simplified to a quarter wave length equivalent counterpart. FIG. 1A shows the convention Doherty architecture during a maximum output power condition, i.e., when both the carrier and the peak amplifiers are in saturation. FIG. 1B shows the architecture in a low power condition wherein the carrier amplifier is operating, but not the peak power amplifier. Thus, the output impedance of the peak amplifier is set a high value (1,000 Ohms).
FIG. 2 is a chart that illustrates the performance of the conventional architecture by showing the bandwidth as a function of return loss at the combining port during the high power condition and the low power condition. In this example, the bandwidth is defined as less than −20 dB return loss. In the lower power mode (when peaking amplifier transistor is OFF and presents high impedance), the return loss of the conventional Doherty architecture only has the requisite bandwidth between 1950 MHz −2050 MHz, i.e., the bandwidth is approximately 100 MHz at 2000 MHz. It shows that the bandwidth limitation is at low power mode. Stated differently, the desired load pull up for main amplifier transistor is only achieved at very narrow frequency band. The conventional Doherty power amplifier is thus inherently narrowband, and is unable to span more than a single band. The bandwidth limitation is due to the combination of transistor technology, matching networks and Doherty combining circuits.
In another approach, an inverted Doherty architecture has been considered. In the inverted scheme, the in-phase signal path includes the peak amplifier and the quadrature signal path includes the carrier amplifier. The Doherty combiner includes a quarter length) (90° phase delay element that has a characteristic impedance that is equal to the load impedance (i.e., Zc=ZL). The delay element and the quadrature signal phase are summed at the combiner node. A second quarter length (90°) phase delay element is disposed between the combiner node and the load; this delay element has a characteristic impedance that is less than the load impedance. The advantage of this scheme is that a 90° transmission lines in the output matching network (for both the in-phase and quadrature paths) is eliminated while maintaining efficiency. The drawback of this approach, is that in the conventional inverted Doherty architecture, the output matching networks are typically designed to transform from transistor impedance directly to load impedance. The impedance transforming ratio is quite very large at this step and bandwidth is limited here by the matching network.
In yet another approach, another inverted Doherty architecture was considered. This scheme is similar to the inverted Doherty approach outlined above, with the exception that the characteristic impedance of the quarter length (90°) phase delay element coupled between the output matching network on the peak signal path and the combiner node is set to a value that is much greater than the load impedance. One significant drawback to this approach is that the carrier signal and the peak amplifier signal will not be efficiently combined at the system output.
Thus, there exists a need for a practical approach at system level that addresses the narrow bandwidth of the conventional Doherty type amplifier, as well as the drawbacks associated with the inverted Doherty configurations described above.